The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device such as a dynamic random access memory (DRAM) comprising one-transistor one-capacitor type memory cells, in which it is possible to reduce the power consumption compared to conventional semiconductor memory devices.
An example of a conventional semiconductor memory device generally comprises a memory cell array, a bit line charge-up circuit, a sense amplifier circuit, an active restore circuit and a column select circuit with respect to a pair of bit lines. The pair of bit lines from the memory cell array are coupled to each of the bit line charge-up circuit, the sense amplifier circuit, the active restore circuit and the column select circuit. The bit line charge-up circuit is used to initially charge the bit lines to a power source voltage. A datum (voltage) is read out from a memory cell within the memory cell array by use of the sense amplifier circuit which senses and amplifies the voltage read out via the bit lines. Hence, a small difference in the potentials at the bit lines is amplified and supplied to the active restore circuit. However, there is an inevitable decrease in the potential when the voltage is read out from the memory cell array by use of the sense amplifier circuit, and the active restore circuit is used to compensate for this decrease in the potential by amplification. Out of a plurality of such amplified signals from a plurality of active restore circuits, the column select circuit selectively passes a signal obtained from one pair of bit lines and supplies this signal to an external data file, for example, via a data bus.
However, a charge-up current or a discharge current in the pair of bit lines can be described by the following equation and is considerably large. EQU [Charge-up current (or discharge current)]=[(Potential at bit line).times.(Capacitance)]/[Time]
Accordingly, in order to reduce the power consumption, semiconductor memory devices have been recently proposed in which the initial charge-up voltage is made less than or equal to one-half the power source voltage. When the initial charge-up voltage is one-half the power source voltage, the charge-up current becomes one-half that of the conventional semiconductor memory device described before.
But as will be described later on in the specification in conjunction with the drawings, when the initial charge-up voltage is reduced to less than or equal to one-half the power source voltage and the active restore circuit of the conventional semiconductor memory device is used as it is, it is extremely difficult to increase the potentials at the bit lines from this reduced charge-up voltage to the power source voltage. As a result, there are problems in that the power consumption of the semiconductor memory device cannot be reduced considerably without introducing undesirable effects on the operation of the semiconductor memory device.